1. Field of Use
The invention relates generally to data processing systems and more specifically to the processing of the scientific ADD instruction in a scientific instruction processor.
2. Description of the Prior Art
Floating point operands include a mantissa, a mantissa sign and an exponent. A scientific processor processes a scientific ADD instruction by comparing the exponents of the operands to determine if they are equal in a first cycle, and shifting the mantissa with the smaller exponent a number of digit positions corresponding to the difference in exponents in a second machine cycle. Such a system is described in U.S. Pat. No. 3,551,665 entitled "Floating Point Binary Adder Utilizing Completely Sequential Hardware."
The Honeywell H800 computing system performed the scientific ADD instruction by testing if the exponents were equal in a first cycle; and if equal, shifting the mantissa one position in a second cycle, then testing the exponents for equal in a third cycle; and if unequal, shifting the mantissa in a fourth cycle. This sequence was repeated until the exponents were equal.
U.S. Pat. No. 4,130,879 entitled "Apparatus for Performing Floating Point Arithmetic Operations Using Submultiple Storage" discloses apparatus for performing a scientific multiply. This same apparatus, when performing the scientific ADD instruction, compares the exponents in a first cycle, shifts the mantissa in a second cycle, and performs the ADD function in a third cycle.
These prior systems have the disadvantage of requiring a relatively large number of cycles for aligning the mantissas when performing the scientific ADD instruction.
It should be understood that the references cited herein are those of which the applicants are aware, and are presented to acquaint the reader with the level of skill in the art, and may not be the closest reference to the invention. No representation is made that any search has been conducted by the applicants.